In a clock signal dividing circuit which divides a clock signal having a frequency to generate a clock signal having a lower frequency, there can be realized a dividing circuit (integer dividing circuit) in which a dividing ratio, i.e., a ratio of a frequency of a clock signal obtained before frequency dividing to a frequency of a clock signal obtained after the frequency dividing is 1/M (M is a positive integer) by using a counter circuit.
On the other hand, a dividing circuit (rational number dividing circuit) which can perform frequency dividing even though a dividing ratio is N/M (N and M are positive integers) is proposed in the past (for example, see Patent Documents 1 and 2). According to the conventional art, values (value N in the dividing ratio N/M) each of which sets a numerator of the dividing ratio are cumulatively added every cycle of an input clock signal. When the addition result is larger than a value (value M in the dividing ratio N/M) which sets a denominator of the dividing ratio, an operation which subtracts M from the addition result is performed, and pulses of the input clock signal are arbitrarily thinned out with reference to the addition result to realize rational number dividing.
As a conventional art, a clock generating circuit using a phase interpolator is proposed (for example, see Patent Document 3). According to the art described in Patent Document 3, an edge is generated by the phase interpolator at a timing except for an edge of an input clock signal to make it possible to generate a rational number divided clock signal having a constant cycle time.    Patent Document 1: Japanese Patent Application Laid-Open No. 2005-45507    Patent Document 2: Japanese Patent Application Laid-Open No. 2006-148807    Patent Document 3: Japanese Patent Application Laid-Open No. 2002-57578